MC56F81663 datasheet(9/73 Pages) NXP

9 / 73 page

• Write-once protection for all registers

• The EVTG module mainly includes two parts: Two AND/OR/INVERT (known

simply as the AOI) modules and one configurable Flip-Flop. It supports the

generation of a configurable number of EVENT signals. The inputs are from crossbar

(XBAR) outputs, and the outputs feed to XBAR inputs.

1.5.9 Quad Timer

• Four 16-bit up/down counters, with a programmable prescaler for each counter

• Operation modes: edge count, gated count, signed count, capture, compare, PWM,

signal shot, single pulse, pulse string, cascaded, quadrature decode

• Programmable input filter

• Counting start can be synchronized across counters

1.5.10 Queued Serial Communications Interface (QSCI) modules with

LIN Slave Functionality

• Operating clock can be up to two times the CPU operating frequency

• Four-word-deep FIFOs available on both transmit and receive buffers

• Standard mark/space non-return-to-zero (NRZ) format

• 16-bit integer and 3-bit fractional baud rate selection

• Full-duplex or single-wire operation

• Programmable 8-bit or 9-bit data format

• Error detection capability

• Two receiver wakeup methods:

• Idle line

• Address mark

• 1/16 bit-time noise detection

• Support for Local Interconnect Network (LIN) slave operation

1.5.11 Queued Serial Peripheral Interface (QSPI) modules

• Maximum 25 Mbit/s baud rate

• Selectable baud rate clock sources for low baud rate communication

• Baud rate as low as the maximum Baud rate / 4096

• Full-duplex operation

• Master and slave modes

• Double-buffered operation with separate transmit and receive registers

• Four-word-deep FIFOs available on transmit and receive buffers

Peripheral highlights

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 数据表(PDF) 9 Page - NXP Semiconductors

MC56F81663 数据表(HTML) 9 Page - NXP Semiconductors

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