MC56F81663 datasheet(7/73 Pages) NXP

7 / 73 page

• Samples of each ADC have offset, limit and zero-crossing calculation supported

• ADC conversions can be synchronized by any module connected to the internal

crossbar module, such as PWM, timer, GPIO, and comparator modules.

• Support for hardware-triggering and software-triggering conversions

• Support for a multi-triggering mode with a programmable number of conversions on

each trigger

• Each ADC has ability to scan and store up to 8 conversion results.

• Current injection protection

1.5.3 Operational Amplifier (OPAMP)

• Up to four sets for rotation configuration

• Configurable gain through internal channels

• Obtain gain through external channels

• Optional clocks for counter

• Low power technology

• Optimize transient response

1.5.4 12-bit Digital-to-Analog Converter

• 12-bit resolution

• Powerdown mode

• Automatic mode allows the DAC to automatically generate pre-programmed output

waveforms, including square, triangle, and sawtooth waveforms (for applications like

slope compensation)

• Programmable period, update rate, and range

• Output can be routed to an internal comparator, or optionally to an off-chip

destination

1.5.5 Comparator

• Full rail-to-rail comparison range

• Support for high and low speed modes

• Selectable input source includes external pins and internal DACs

• Programmable output polarity

• 8-bit programmable DAC as a voltage reference per comparator

• Three programmable hysteresis levels

• Selectable interrupt on rising-edge, falling-edge, or toggle of a comparator output

Peripheral highlights

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 数据表(PDF) 7 Page - NXP Semiconductors

MC56F81663 数据表(HTML) 7 Page - NXP Semiconductors

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