MC56F81663 datasheet(57/73 Pages) NXP

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11.5.1.1 Equivalent circuit for ADC inputs

The following figure shows the ADC input circuit during sample and hold. S1 and S2 are

always opened/closed at non-overlapping phases, and both S1 and S2 are dependent on

the ADC clock frequency. The following equation gives equivalent input impedance

when the input is selected.

Freescale Semiconductor



(ADC ClockRate) x CADI

+Resistor

ohm

NOTE

Resistor=1200 ohm@gain1×, or 730 ohm@gain2×, or 500

ohm@gain4×



Analog Input

S/H

(VREFHx - VREFLx ) / 2

50  ESD

Resisto

Channel Mux

equivalent resistance

Resistor(value see the note)

1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =

1.8pF

2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal

routing = 2.04pF

3. S1 and S2 switch phases are non-overlapping and depend on the ADC clock

frequency



S 1

S 2

Figure 11. Equivalent circuit for A/D loading

System modules

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

MC56F81663 数据表(PDF) 57 Page - NXP Semiconductors

MC56F81663 数据表(HTML) 57 Page - NXP Semiconductors

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