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MC56F81663 数据表(PDF) 5 Page - NXP Semiconductors

部件名 MC56F81663
功能描述  DSC based on 32-bit 56800EX core
PDF  73 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MC56F81663 数据表(HTML) 5 Page - NXP Semiconductors

  MC56F81663 Datasheet HTML 1Page - NXP Semiconductors MC56F81663 Datasheet HTML 2Page - NXP Semiconductors MC56F81663 Datasheet HTML 3Page - NXP Semiconductors MC56F81663 Datasheet HTML 4Page - NXP Semiconductors MC56F81663 Datasheet HTML 5Page - NXP Semiconductors MC56F81663 Datasheet HTML 6Page - NXP Semiconductors MC56F81663 Datasheet HTML 7Page - NXP Semiconductors MC56F81663 Datasheet HTML 8Page - NXP Semiconductors MC56F81663 Datasheet HTML 9Page - NXP Semiconductors Next Button
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V Temperature option:-40 oC to 105oC
M Temperature option:-40 oC to 125oC
• Single 3.3 V power supply
• Supply range: VDD - VSS = 2.7 V to 3.6 V, VDDA - VSSA = 2.7 V to 3.6 V
1.4 Interrupt Controller
• Five interrupt priority levels
• Three user-programmable priority levels for each interrupt source: level 0, level
1, level 2
• Unmaskable level 3 interrupts include illegal instruction, hardware stack
overflow, misaligned data access, SWI3 instruction
• Interrupt level 3 is highest priority and non-maskable. Its sources include:
• Illegal instructions
• Hardware stack overflow
• SWI instruction
• EOnce interrupts
• Misaligned data accesses
• Lowest-priority software interrupt: level LP
• Support for nested interrupts, so that a higher priority level interrupt request can
interrupt lower priority interrupt subroutine
• Masking of interrupt priority level is managed by the 56800EX core
• Two programmable fast interrupts that can be assigned to any interrupt source
• Notification to System Integration Module (SIM) to restart clock when in wait and
stop states
• Ability to relocate interrupt vector table
Peripheral highlights
1.5.1 Enhanced Flex Pulse Width Modulator (eFlexPWM)
• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs
• PWMA with NanoEdge high resolution
• Fractional delay for enhanced resolution of the PWM period and edge placement
• Arbitrary PWM edge placement
• 312 ps PWM frequency and duty-cycle resolution when NanoEdge functionality
is enabled.
• PWM outputs can be configured as complementary output pairs or independent
outputs
1.5
Peripheral highlights
MC56F81xxx, Rev. 1.1, 12/2020
NXP Semiconductors
5



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