MC56F81663 datasheet(44/73 Pages) NXP

44 / 73 page

Table 11. Power mode transition behavior (continued)

Symbol

Description

Typical

Max

Unit

Notes1

LPS mode to LPRUN mode

285

328

µs

VLPS mode to VLPRUN mode

878

1010

µs

WAIT mode to RUN mode

0.395

0.454

µs

LPWAIT mode to LPRUN mode

285

328

µs

VLPWAIT mode to VLPRUN mode

868

998

µs

1. Wakeup times are measured from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from

respective stop/wait mode.

2. Clock configuration: CPU clock=4 MHz. System clock source is 8 MHz IRC in normal mode.

3. CPU clock = 200 kHz and 8 MHz IRC on standby. Exit by an interrupt on PORTA GPIO.

4. Using 64 kHz external clock; CPU Clock = 32 kHz. Exit by an interrupt on PORTA GPIO.

5. Clock configuration: CPU and system clocks= 100 MHz. Bus Clock = 50MHz. Exit by interrupt on PORTA GPIO

10.3.5 Power consumption operating behaviors

Table 12. Current Consumption (Unit: mA)

Mode

Maximum

Frequency

Conditions

Typical at

3.3 V,

25°C

Maximum

at 3.6 V,

105°C

Maximum

at 3.6V,

125°C

IDD1 IDDA IDD1 IDDA IDD1 IDDA

RUN1

100 MHz

• 100 MHz Core

• 50 MHz Peripheral clock

• Regulators are in full regulation

• Relaxation Oscillator on

• PLL powered on

• Continuous MAC instructions with fetches from

Program Flash

• All peripheral modules enabled. TMRs and SCIs

using 1X peripheral clock

• NanoEdge within eFlexPWM using 2X peripheral

clock

• ADC/DAC (only one 12-bit DAC and all 8-bit DACs)

powered on and clocked

• Comparator powered on

24.9

8.6

46.0 13.2 46.9 13.2

RUN2

50 MHz

• 50 MHz Core and Peripheral clock

• Regulators are in full regulation

• Relaxation Oscillator on

• PLL powered on

• Continuous MAC instructions with fetches from

Program Flash

• All peripheral modules enabled. TMRs and SCIs

using 1X peripheral clock

• NanoEdge within eFlexPWM using 2X peripheral

clock

• ADC/DAC (only one 12-bit DAC and all 8-bit DACs)

powered on and clocked

• Comparator powered on

20.3

8.7

43.0 12.2 43.4 12.3

WAIT

50 MHz

• 50 MHz Core and Peripheral clock

17.3

—

35.0

—

35.7

—

Table continues on the next page...

General

MC56F81xxx, Rev. 1.1, 12/2020

NXP Semiconductors

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