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LSM6DSTX 数据表(PDF) 123 Page - STMicroelectronics |
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LSM6DSTX 数据表(HTML) 123 Page - STMicroelectronics |
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123 / 175 page ![]() 13.41 EMB_FUNC_ODR_CFG_C (60h) Machine learning core output data rate configuration register (R/W) Table 309. EMB_FUNC_ODR_CFG_C register 0(1) 0(1) MLC_ODR1 MLC_ODR0 0(1) 1(2) 0(1) 1(2) 1. This bit must be set to 0 for the correct operation of the device. 2. This bit must be set to 1 for the correct operation of the device. Table 310. EMB_FUNC_ODR_CFG_C register description MLC_ODR[1:0] Machine learning core ODR configuration: (00: 12.5 Hz; 01: 26 Hz (default); 10: 52 Hz; 11: 104 Hz) 13.42 STEP_COUNTER_L (62h) and STEP_COUNTER_H (63h) Step counter output register (R) Table 311. STEP_COUNTER_L register STEP_07 STEP_06 STEP_05 STEP_04 STEP_03 STEP_02 STEP_01 STEP_0 Table 312. STEP_COUNTER_L register description STEP_[7:0] Step counter output (LSbyte) Table 313. STEP_COUNTER_H register STEP_15 STEP_14 STEP_13 STEP_12 STEP_11 STEP_10 STEP_09 STEP_8 Table 314. STEP_COUNTER_H register description STEP_[15:8] Step counter output (MSbyte) LSM6DSTX EMB_FUNC_ODR_CFG_C (60h) DS14039 - Rev 1 page 123/175 |
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