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ADC3908CSSS 数据表(PDF) 14 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 14 Page - Texas Instruments |
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14 / 131 page ![]() 5.11 Output Interface Timing Diagram B0 B1 B8 B9 B0 B1 B8 B9 Sampling Clock Sample N tAD tPD DCLK Sample N D11 Sample N-1 Sample N+1 Input Signal D03 D02 D10 A9 A8 A1 A0 tS TDCLK A9 A8 A1 A0 tH DCLK tACQ tCONV Figure 5-1. Timing Diagram: 10-Bit DDR (Default: 10 Lanes) ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 14 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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