ADC3908CSSS datasheet(34/131 Pages) TI1

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6.3.3 Sampling Clock Input

The ADC3910Dx and ADC3910Sx has a single-ended sampling clock input. To maximize the ADC SNR

performance, the external sampling clock can have low jitter with a high slew rate. The ADC3910Dx and

ADC3910Sx can be AC or DC coupled externally. When AC coupling sampling clock needs to have a resistor

divider such that the center voltage is around 0.9 V and when DC coupling the sampling clock, center voltage

needs to be around 0.9 V as shown in Figure 6-6.

CLK

0.9V

1.8V

ADC

AVDD

GND

Figure 6-6. Sampling clock configuration: AC coupled (left) and DC coupled (right)

6.3.4 Voltage Reference

ADC3910Dx and ADC3910Sx by default is set to internal reference. For highest accuracy and lowest

temperature drift, the ADC3910Dx and ADC3910Sx provides an option to supply a external reference voltage

to the ADC. A 10 µF and a 0.1 µF ceramic bypass capacitor connected between VREF and GND pins, and

placed as close to the pins as possible is recommended when using an external reference. Otherwise, the VREF

pin should be connected to ground when using the internal reference. The internal reference circuitry of the

ADC3910Dx and ADC3910Sx is shown in Figure 6-7.

Note

The voltage reference mode can be selected using SPI write in register in 0x30B.

REF

ADC

INxP

INxM

VCM

REFIO

REFERENCE

1.2 V

Figure 6-7. External 1.2 V reference

6.3.5 Over-range (OVR)

The ALERT by default is configured to trigger when either ADC channel A or ADC channel B detects a signal

over-range on the input. The ALERT pin can also be configured via SPI write to register ALERT_PIN_SEL

(0x09C) to ignore one of the ADC channels or to trigger when a digital alert is detected, including if an

over-range is detected within a digital block. See the Digital Alert section to configure additional triggers in the

digital features.

ADC3910D125

SBASAD1 – DECEMBER 2023

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