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ADC3908CSSS 数据表(PDF) 40 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 40 Page - Texas Instruments |
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40 / 131 page  Table 6-3. Serial CMOS Lane Rate Examples with Real Decimation and 16-bit Output Resolution Decimation Output Resolution Lanes Serialization DCLK FCLK Bypass 10 bits 10 1 FS N/A 12 bits 12 1 FS N/A /2 16 bits 8 2 FS FS / 4 /4 8 2 FS / 2 FS / 8 4 4 FS FS / 8 /8 8 2 FS / 4 FS / 16 4 4 FS / 2 FS / 16 2 8 FS FS / 16 /16 8 2 FS / 8 FS / 32 4 4 FS / 4 FS / 32 2 8 FS / 2 FS / 32 Note 16 bit resolution does not support a serialization factor of 1. B0 B1 B6 B7 B8 B9 B14 B15 DCLK Sample N D11 D05 D04 D10 A15 A14 A9 A8 A7 A6 A1 A0 DDR DEFAULT 8 Lane 2x Serializa on B8 B9 B14 B15 B0 B1 B6 B7 A0 A1 A6 A7 DCLK Sample N D11 D05 D04 D10 A15 A14 A9 A8 FCLK DDR 8 Lane 2x Serializa on B12 B15 B4 B5 A4 A7 B0 B2 A0 A3 B8 B8 A8 A11 Sample N D11 D05 D02 D08 A15 A12 DCLK HDDR 8 Lane 2x Serializa on B12 B15 B4 B5 A4 A7 B0 B2 A0 A3 B8 B8 A8 A11 Sample N D11 D07 D04 D08 A15 A12 DCLK SDR 8 Lane 2x Serializa on FCLK FCLK FCLK Figure 6-21. 16 Bit, 8 Lanes, 2x Serialization ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 40 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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