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ADC3908CSSS 数据表(PDF) 61 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 61 Page - Texas Instruments |
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61 / 131 page  Table 6-29. INTERFACE_CFG_1 Register Field Descriptions (continued) Bit Field Type Reset Description 5 HDDR_EN R/W 0h Enable HDDR interface mode 0b = HDDR interface mode disabled 1b = HDDR interface mode enabled 4 SDR_EN R/W 0h Enable SDR interface mode 0b = SDR interface mode disabled 1b = SDR interface mode enabled 3:0 ALERT_PIN_STRENGTH R/W 0h ALERT output pin strength 0000b = 15/15 (default) 0001b = 14/15 0010b = 13/15 0011b = 12/15 0100b = 11/15 0101b = 10/15 0110b = 9/15 0111b = 8/15 1000b = 7/15 1001b = 6/15 1010b = 5/15 1011b = 4/15 1100b = 3/15 1101b = 2/15 1110b = 1/15 1111b = 0/15 (Tri-state) 6.6.1.24 INTERFACE_CFG_2 Register (Address = 9Ch) [Reset = 00h] Return to the Summary Table. Table 6-30. INTERFACE_CFG_2 Register Field Descriptions Bit Field Type Reset Description 6 OENZ_GPDN R/W 0h Overwrites OENZ control pin as global power down. Global power down superseeds fast power down. 0b = OENZ control pin functions as output enable 1b = OENZ control pin functions as global power down 5 OENZ_FPDN R/W 0h Overwrites OENZ control pin as fast power down. Global power down superseeds fast power down. 0b = OENZ control pin functions as output enable 1b = OENZ control pin functions as fast power down 4:2 RESERVED R 0h 1:0 ALERT_PIN_SEL R/W 0h Alert output pin function. By default the ALERT output pin monitors overranging at the ADC core. 00b = Channel A overrange (OVR CHA) || Channel B overrange (OVR CHB) 01b = Channel A overrange (OVR CHA) 10b = Channel B overrange (OVR CHB) 11b = Digital Alerts 6.6.1.25 HFSB_FPDN_CFG Register (Address = 9Eh) [Reset = 00h] Return to the Summary Table. Table 6-31. HFSB_FPDN_CFG Register Field Descriptions Bit Field Type Reset Description 6:5 HFSB_CONFIG R/W 0h DCLK generation block control. Used when global HFSB is 0 (CLK is greater than 65 MSPS) and DCLK is less than 65 MSPS, e.g. decimation. Forces half speed mode on DCLK generation block. 00b = Half speed mode for DCLK disabled 11b = Half speed mode for DCLK enabled www.ti.com ADC3910D125 SBASAD1 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 61 Product Folder Links: ADC3910D125 |
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