 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADC3908CSSS 数据表(PDF) 62 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADC3908CSSS 数据表(HTML) 62 Page - Texas Instruments |
|
|
62 / 131 page  Table 6-31. HFSB_FPDN_CFG Register Field Descriptions (continued) Bit Field Type Reset Description 4 PDN_FAST R/W 0h Fast power down via SPI. 0b = Fast power down disabled 1b = Fast power down enabled. Power down mask (register 0x008C) determines which internal blocks are powered down. 3:0 RESERVED R 0h 6.6.1.26 INTERFACE_CFG_3 Register (Address = A0h) [Reset = 00h] Return to the Summary Table. Table 6-32. INTERFACE_CFG_3 Register Field Descriptions Bit Field Type Reset Description 5 CHB_SWAP R/W 0h Selects the channel data to send on Channel B output. Applicable in DDR interface mode and only available when digital enabled. 0b = Channel B data on channel B output 1b = Channel A data on channel B output 4 CHA_SWAP R/W 0h Selects the channel data to send on Channel A output. Applicable in DDR interface mode and only available when digital enabled. 0b = Channel A data on channel A output 1b = Channel B data on channel A output 3 OENZ_PIN_VAL R/W 0h Value to be overwritten on OENZ pin. Must enable OENZ overwrite in register 0x00A0, bit 2. 2 OENZ_PIN_OW R/W 0h OENZ pin overwrite 0b = Use value on OENZ pin 1b = Use value from OENZ_PIN_ VAL. Ignore value on OENZ pin. 1:0 RESERVED R 0h 6.6.1.27 DIG_PATTERN_EN Register (Address = A1h) [Reset = 00h] Return to the Summary Table. Table 6-33. DIG_PATTERN_EN Register Field Descriptions Bit Field Type Reset Description 5:3 DIG_PATTERN_MODE_C HB R/W 0h Enables test pattern output mode for channel B. 001b = Ramp pattern with step size of 1 010b = Ramp pattern with step size set in DIG PAT CHA 100b = Constant pattern using DIG PAT CHA 101b = Toggle pattern between DIG PAT CHA and bitwise inverted DIG PAT CHA 110b = Toggle pattern between DIG PAT CHA and 0 2:0 DIG_PATTERN_MODE_C HA R/W 0h Enables test pattern output mode for channel A. 001b = Ramp pattern with step size of 1 010b = Ramp pattern with step size set in DIG PAT CHA 100b = Constant pattern using DIG PAT CHA 101b = Toggle pattern between DIG PAT CHA and bitwise inverted DIG PAT CHA 110b = Toggle pattern between DIG PAT CHA and 0 6.6.1.28 DIG_PATTERN_CHA_7:0 Register (Address = A2h) [Reset = 00h] Return to the Summary Table. ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 62 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
