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ADC3908CSSS 数据表(PDF) 64 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 64 Page - Texas Instruments |
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64 / 131 page  6.6.1.33 OUTPUT_DATA_WIDTH Register (Address = A7h) [Reset = 50h] Return to the Summary Table. Table 6-39. OUTPUT_DATA_WIDTH Register Field Descriptions Bit Field Type Reset Description 4:0 OUTPUT_DATA_WIDTH R/W Ah Output resolution for lane optimization in serialization modes. 01000b = 8-bit 01010b = 10-bit 01100b = 12-bit 10000b = 16-bit 6.6.1.34 DCLK_DIVIDER Register (Address = A8h) [Reset = 0h] Return to the Summary Table. Table 6-40. DCLK_DIVIDER Register Field Descriptions Bit Field Type Reset Description 3:0 DCLK_DIVIDER R/W 0h Division of CLK to DCLK to match serialization and decimation data rates. Decimation and serialization factor (SERIALIZATION) must match. 0000b = Divide-by-1 0001b = Divide-by-2 0011b = Divide-by-4 0111b = Divide-by-8 1111b = Divide-by-16 6.6.1.35 OUTPUT_BIT_MAPPER_D0_D1 Register (Address = AEh) [Reset = D6h] Return to the Summary Table. Table 6-41. OUTPUT_BIT_MAPPER_D0_D1 Register Field Descriptions Bit Field Type Reset Description 7:4 OUTPUT_BIT_MAPPER_ D1 R/W Dh These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB) 3:0 OUTPUT_BIT_MAPPER_ D0 R/W 6h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB) ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 64 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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