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ADC3908CSSS 数据表(PDF) 54 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 54 Page - Texas Instruments |
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54 / 131 page  Complex bit access types are encoded to fit into small table cells. Table 6-6 shows the codes that are used for access types in this section. Table 6-6. Device Access Type Codes Access Type Code Description Read Type R R Read Write Type W W Write Reset or Default Value -n Value after reset or the default value 6.6.1.1 RESET Register (Address = 0h) [Reset = 00h] Return to the Summary Table. Table 6-7. RESET Register Field Descriptions Bit Field Type Reset Description 7 RESET W 0h This bit resets all internal registers to the default values and self clears to 0. 6:0 RESERVED R 0h 6.6.1.2 CFG_ALERT Register (Address = 38h) [Reset = 0h] Return to the Summary Table. Table 6-8. CFG_ALERT Register Field Descriptions Bit Field Type Reset Description 0 CFG_ALERT R 0h Indicates that the device is ready to be configured. The user can poll this bit before starting the device configuration. Alternatively, the user can wait for a fixed time (2000 clock cycles) after reset release before triggering device configuration 6.6.1.3 SPARE_REG Register (Address = 39h) [Reset = 00h] Return to the Summary Table. Table 6-9. SPARE_REG Register Field Descriptions Bit Field Type Reset Description 7:0 SPARE_REG R/W 0h This field has no functionality and can be used for validating SPI writes. 6.6.1.4 INTERLEAVE Register (Address = 84h) [Reset = 0h] Return to the Summary Table. ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 54 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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