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ADC3908CSSS 数据表(PDF) 71 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 71 Page - Texas Instruments |
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71 / 131 page  Table 6-61. DECIMATION Register Field Descriptions Bit Field Type Reset Description 3 DDC_CHB R/W 0h Channel B decimation 0b = Decimation disabled 1b = Decimation enabled 2 DDC_CHA R/W 0h Channel A decimation 0b = Decimation disabled 1b = Decimation enabled 1:0 RESERVED R 0h 6.6.1.56 PROG_GAIN_CHA Register (Address = D5h) [Reset = 00h] Return to the Summary Table. Table 6-62. PROG_GAIN_CHA Register Field Descriptions Bit Field Type Reset Description 7:0 PROG_GAIN_CHA R/W 0h Programmable gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15. 6.6.1.57 PROG_GAIN_CHB Register (Address = D6h) [Reset = 00h] Return to the Summary Table. Table 6-63. PROG_GAIN_CHB Register Field Descriptions Bit Field Type Reset Description 7:0 PROG_GAIN_CHB R/W 0h Programmable gain for channel B. Effective gain = (PROG GAIN CHB * 256 + IL GAIN CHB)/2**15 6.6.1.58 IL_GAIN_CHA_7:0 Register (Address = D8h) [Reset = 00h] Return to the Summary Table. Table 6-64. IL_GAIN_CHA_7:0 Register Field Descriptions Bit Field Type Reset Description 7:0 IL_GAIN_CHA__7:0 R/W 0h Interleaving gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15 6.6.1.59 IL_GAIN_CHA_15:8 Register (Address = D9h) [Reset = 00h] Return to the Summary Table. Table 6-65. IL_GAIN_CHA_15:8 Register Field Descriptions Bit Field Type Reset Description 7:0 IL_GAIN_CHA__15:8 R/W 0h Interleaving gain for channel A. Effective gain = (PROG GAIN CHA * 256 + IL GAIN CHA)/2**15 6.6.1.60 IL_GAIN_CHB_7:0 Register (Address = DAh) [Reset = 00h] Return to the Summary Table. www.ti.com ADC3910D125 SBASAD1 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 71 Product Folder Links: ADC3910D125 |
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