ADC3908CSSS datasheet(77/131 Pages) TI1

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Table 6-85. BUF_CURR Register Field Descriptions (continued)

Bit

Field

Type

Reset

Description

5:2

BUF_CURR_CHA

R/W

ADC channel A input buffer PTAT current source mask used for gain

tracking across temperature for stability.

0000b = 19.9uA (default)

0001b = 26.5uA

0010b = 13.3uA

0011b = 19.9uA

0100b = 29.9uA

0101b = 36.5uA

0110b = 23.3uA

0111b = 29.9uA

1000b = 6.6uA

1001b = 13.2uA

1010b = 0uA

1011b = 6.6uA

1100b = 16.6uA

1101b = 23.2uA

1110b = 10uA

1111b = 16.6uA

1:0

BUF_CURR_CHB__3:2

R/W

ADC channel B input buffer PTAT current source mask LSB's used

for gain tracking across temperature for stability.

00b = 19.9uA (default)

01b = 26.5uA

10b = 13.3uA

11b = 19.9uA

100b = 29.9uA

101b = 36.5uA

110b = 23.3uA

111b = 29.9uA

1000b = 6.6uA

1001b = 13.2uA

1010b = 0uA

1011b = 6.6uA

1100b = 16.6uA

1101b = 23.2uA

1110b = 10uA

1111b = 16.6uA

6.6.1.80 DEV_CFG_4 Register (Address = 30Bh) [Reset = 00h]

Return to the Summary Table.

Table 6-86. DEV_CFG_4 Register Field Descriptions

Bit

Field

Type

Reset

Description

EXT_REF

R/W

Selects the voltage reference option

0b = Internal reference

1b = External reference

SE_EN

R/W

Single ended analog input for ADC channels A and B. In this mode

the SNR reduces by 3-dB.

0b = Differential input

1b = Single ended input

SINGLE_CH

R/W

Disables ADC channel B

0b = ADC channel B enabled

1b = ADC channel B disabled (enforced on single channel devices)

RESERVED

HALF_SPEED

R/W

Half speed mode (HFSB). Enable when sample clock is less than 65

MSPS.

0b = Half speed mode disabled

1b = Half speed mode enabled (enforced on 25MSPS and 65MSPS

devices)

RESERVED

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