ADC3908CSSS datasheet(48/131 Pages) TI1

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6.3.7 Digital Interface

The ADC39xx family supports multiple CMOS output modes - parallel DDR/HDDR, SDR, and serialized CMOS

output formats. The output data can be configured to two's complement (default) or offset binary via SPI write

(0x30A).

6.3.7.1 Parallel CMOS Output

The ADC3910Dx and ADC3910Sx supports double data rate (DDR), half double data rate (HDDR), and single

data rate (SDR). In DDR/HDDR mode, the device generates the output data clock along with inverse data clock.

Single channel ADCs can use SDR mode where data is output on the rising edge of the clock.

By default, DDR mode clocks output data by alternating channel A data on the rising and channel B data on the

falling edge on the same lane. This behavior can be changed to clock all of channel A data first and then channel

B data via SPI write to DDR_MODE (0x0A6). HDDR mode clocks channel A data on separate output lanes from

channel B data via SPI write to HDDR_EN (0x098).

For receivers that cannot clock data on the falling edge of data clock, inverse data clock can be used to clock

data on rising edge.

See Section 5.11 section for timing diagrams for parallel CMOS output.

6.3.7.2 Serialized CMOS Output

In this operation, the output data is serialized and transmitted over fewer lanes. Due to CMOS output speed

limitation, the operation is only available for reduced output data rates. See the Section 6.3.6.1.4 section for

details on serial CMOS output.

6.3.8 Test Patterns

To enable in-circuit testing of the digital interface, the following test patterns are supported and enabled via SPI

using the DDC, statistics engine or comparator functions and a second available in low latency (digital bypassed)

mode.

ADC

Dig Test

Pattern

Output

Formatter

16/12/10/8-bit

DIG

I/F

Output

Bit Mapper

Channel

Correction

Statistics

Engine

ALERT

Test

Pattern

Comparator

SPI I/F

Figure 6-32. Test pattern block diagram

ADC3910D125

SBASAD1 – DECEMBER 2023

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