ADC3908CSSS datasheet(24/131 Pages) TI1

部件名	ADC3908CSSS

功能描述	ADC3910Dx and ADC3910Sx 10-bit, 25 to 125-MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers

PDF	131 Pages

Scroll/Zoom	100%

制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

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5.13 Typical Characteristics - 65MSPS (continued)

Typical values at TA = 25 °C, ADC sampling rate = 65 MSPS, AIN = –1 dBFS, differential input, AVDD = IOVDD = 1.8 V,

internal 1.2 V voltage reference, unless otherwise noted.

Code

128

256

384

512

640

768

896

1024

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

Ext REF

Int REF

FIN = 5 MHz

Figure 5-36. INL vs ADC Code

Code

128

256

384

512

640

768

896

1024

-0.4

-0.2

0.2

0.4

Ext REF

Int REF

FIN = 5 MHz

Figure 5-37. DNL vs ADC Code

Output Code

20%

40%

60%

80%

100%

508

509

510

511

512

513

514

515

516

517

Figure 5-38. DC Offset Histogram

Samples

4096

8192

12288

16384

20480

24576

28672

32768

128

256

384

512

640

768

896

1024

Pulse Input = 1 MHz

Figure 5-39. Pulse Response

Sample Rate (MSPS)

IAVDD, 2-ch.

IAVDD, 1-ch.

IOVDD, 2-ch., DDR

IOVDD, 1-ch., DDR

IOVDD, 1-ch., SDR

FIN = 5 MHz, DDC Bypass

Figure 5-40. Current vs Sampling Rate

Decimation

AVDD 25MSPS

IOVDD 25MSPS

AVDD 65MSPS

IOVDD 65MSPS

AVDD 125MSPS

IOVDD 125MSPS

FIN = 1 MHz, 16 bit resolution, DDR, 8 Output Lanes

Figure 5-41. Current vs Decimation

ADC3910D125

SBASAD1 – DECEMBER 2023

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