ADC3908CSSS datasheet(31/131 Pages) TI1

31 / 131 page

6.3 Feature Description

6.3.1 ADC Features

6.3.1.1 Low Latency Mode

By default the ADC3910Dx and ADC3910Sx are in low latency mode where all digital features such as

decimation, statistics engine and comparator are disabled and the interface is set to DDR, 10 output lanes.

In this mode, latency between the ADC input and digital output is 1 clock cycle. Enabling any digital features or

changing the interface mode adds latency to the device throughput.

6.3.1.2 Full Digital Feature Mode

With the digital features enabled the ADC3910Dx and ADC3910Sx offers the ability to decimate, on-chip

comparators, statistics engines and configurable alerts. See the Digital Features and Digital Interface sections

for details on to set up each of these options.

Note

Enabling the digital features adds additional ADC latency depending on the configuration.

ADC

Dig Test

Pattern

Output

Formatter

16/12/10/8-bit

DIG

I/F

Output

Bit Mapper

Channel

Correction

Statistics

Engine

ALERT

Test

Pattern

Comparator

SPI I/F

Figure 6-1. Digital features block diagram

6.3.1.3 Interleaving Mode

The ADC3910Dx can be used as a single-channel ADC where the sampling rate is equal to two times the

clock frequency (FS = 2 × FCLK). This mode interleaves the two channels by sampling them out-of-phase.

Figure 6-2 shows block diagram when interleaving mode is selected. Operating in interleaving mode disables the

digital down converter, statistics engine, and digital comparator. Interleaving mode supports only parallel output

interface.

Note

Interleaving is only available on dual channel ADCs. Single channel ADCs do not have the ability to

interleave.

Interleaving can be enabled in SPI register INTERLEAVE (0x84). Offset, gain, and timing controls are available

in SPI registers OFFSET_CHx, PROG_GAIN_CHx, IL_GAIN_CHx, and CLK_TIM_ADJ_CHx (0x0D5-0x0DF) to

minimize mismatches between the ADCs. Channel corrections (offset, gain) must be enabled in SPI register

CORR_CHx (0x0E0). Enabling channel corrections add several clock cycles of latency.

www.ti.com

ADC3910D125

SBASAD1 – DECEMBER 2023

Submit Document Feedback

Product Folder Links: ADC3910D125

ADC3908CSSS 数据表(PDF) 31 Page - Texas Instruments

ADC3908CSSS 数据表(HTML) 31 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载