ADC3908CSSS datasheet(39/131 Pages) TI1

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Decimation Mode

62.5

67.5

72.5

25MSPS

65MSPS

125MSPS

FIN = 1 MHz, AIN = -1dBFS, 16-bit resolution mode

Figure 6-20. SNR Performance vs Decimation Mode

6.3.6.1.3 DDC Over-range

The ADC3910Dx and ADC3910Sx has an overrange indicator that can be enabled via SPI write to register

0x205-0x206 to protect the analog inputs from being saturated for extended period of time since latency is

increased with decimation. When the alert pin is asserted, it stays high for one clock cycle of FOUT (FS divided by

decimation factor) and then de-asserted.

6.3.6.1.4 Output Formatting with Decimation

In serial CMOS mode, the ADC3910Dx and ADC3910Sx has a configurable output data mapping. Default bit

size in serial CMOS is 10 bits wide and interface default is set to DDR. Interface options are double data rate

(DDR), half double data rate (HDDR), and single data rate (SDR) via SPI write to register 0x098.

By default DDR mode clocks output data by alternating channel A data on the rising and channel B data on

the falling edge of DCLK on the same lane. This behavior can be changed to clock all of channel A data first

and then channel B data via SPI write to DDR_MODE (0x0A6). HDDR mode clocks channel A data on separate

output lanes from channel B data via SPI write to HDDR_EN (0x098).

SDR mode clocks data only on rising edge; therefore, to clock both data samples in a cycle, requires double the

data clock speed. The following diagrams show the different available configurations that can be programmed,

and Table 6-3 shows actual data and clock rates.

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ADC3910D125

SBASAD1 – DECEMBER 2023

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ADC3908CSSS 数据表(PDF) 39 Page - Texas Instruments