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ADC3908CSSS 数据表(PDF) 58 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 58 Page - Texas Instruments |
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58 / 131 page  Table 6-18. DEV_CFG_3 Register Field Descriptions (continued) Bit Field Type Reset Description 3 DCLKZ_DLL R/W 0h Swap DCLKZ_OUT to DCLK output of DLL 0b = DCLKZ_OUT to DCLKZ output of DLL 1b = DCLKZ_OUT to DCLK output of DLL 2 DCLK_DLL R/W 0h Swap DCLK_OUT to DCLKZ output of DLL 0b = DCLK_OUT to DCLK output of DLL 1b = DCLK_OUT to DCLKZ output of DLL 1 ALERT_POL R/W 0h ALERT pin polarity 0b = ALERT pin active high 1b = ALERT pin active low 0 RESERVED R 0h 6.6.1.13 CLK_CFG_3 Register (Address = 8Eh) [Reset = 00h] Return to the Summary Table. Table 6-19. CLK_CFG_3 Register Field Descriptions Bit Field Type Reset Description 7:6 DCLK_SYNC R/W 0h Used for DDR and SDR interface modes 00b = DDR Clocking mode (DCLKZ is inversion of DCLK) 01b = DDR Clocking 1010b = SDR Clocking (DCLKZ is same as DCLK) 1011b = DCLK/DCLKZ off 5:2 RESERVED R 0h 1 ADLL_BYP R/W 0h Bypass analog DLL. Enable this setting for low frequency input signals below 25 MHz. Reduces current by 1 mA. 0b = Normal operation 1b = Analog DLL bypassed 0 RESERVED R 0h 6.6.1.14 CLK_CFG_4 Register (Address = 8Fh) [Reset = 00h] Return to the Summary Table. Table 6-20. CLK_CFG_4 Register Field Descriptions Bit Field Type Reset Description 6 RESERVED R 0h Reserved 5 RESERVED R 0h Reserved 4 DCLK_DLL R/W 0h Enable when digital features are used 3:0 RESERVED R 0h 6.6.1.15 PIN_CFG_1 Register (Address = 90h) [Reset = 00h] Return to the Summary Table. Table 6-21. PIN_CFG_1 Register Field Descriptions Bit Field Type Reset Description 7 ALERT_OD R/W 0h Alert output pin mode 0b = Push-pull 1b = Open-drain 6:4 RESERVED R 0h ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 58 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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