ADC3908CSSS datasheet(30/131 Pages) TI1

30 / 131 page

6 Detailed Description

6.1 Overview

The ADC3910Dx and ADC3910Sx are a family of ultra-low power 10-bit high-speed dual and single channel

analog-to-digital converters supporting sampling rates up to 125 MSPS. With the inherent low latency

architecture, the digital output result is available after only one clock cycle in low latency mode. The ADC3910Dx

and ADC3910Sx has buffered analog inputs which eases design by isolating the input from the ADC sampling

operation and supports single ended or differential input signaling. The ADC3910Dx and ADC3910Sx are

equipped with an on-chip internal reference buffer but also supports use of an external, high precision 1.2 V

voltage reference.

The ADC3910Dx and ADC3910Sx also offers several digital features such as:

• Digital down converters that enables external anti-alias filter relaxation as well as output data rate reduction.

The digital filter supports only real decimation.

• Digital comparators with a dedicated alert pin that can be used to interrupt the host when a programmed high

or low threshold is crossed on any input channel.

• Statistics engine that provides min, max, sum, sum of samples squared, and threshold triggered counter, that

will give additional sample details.

The CMOS output data interface can be configured in parallel or serial with the option of 1.8 V to 3.3 V logic.

The device supports DDR, SDR and Serial CMOS modes with 2s Complement or Offset Binary format options.

The ADC3910Dx and ADC3910Sx offers DCLK as an alternate solution for designs that can not capture on the

DCLK falling edge when using DDR interface.

Table 6-1 shows the pin mapping to supply.

Table 6-1. Device Pin to Supply Mapping

Power Supply

Device Pins

AVDD

OEN, DCLKIN, CLK, INxP|M, RESET, SDIO, SCLK, SEN

IOVDD

D0-D11, DCLK, DCLK|FCLK, ALERT

6.2 Functional Block Diagram

REF

ADC

Digital Comparator

RESET

AVDD

ALERT/GPO

IOVDD

CLK

GND

INAP

INAM

INBP

INBM

VCM

VREF

High/Low Threshold

± Hysteresis

Flexible

Data

Interface

Control

Interface

DDC

DCLKIN

DCLK

DCLK/FCLK

D11-D0

SEN

SCLK

SDIO

Statistics

Engine

ADC3910D125

SBASAD1 – DECEMBER 2023

www.ti.com

Submit Document Feedback

Product Folder Links: ADC3910D125

ADC3908CSSS 数据表(PDF) 30 Page - Texas Instruments

ADC3908CSSS 数据表(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载