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ADC3908CSSS 数据表(PDF) 63 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 63 Page - Texas Instruments |
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63 / 131 page  Table 6-34. DIG_PATTERN_CHA_7:0 Register Field Descriptions Bit Field Type Reset Description 7:0 DIG_PATTERN_CHA__7: 0 R/W 0h Used with DIG PAT MODE CHA to set constant custom pattern starting from MSB or sets ramp pattern increment step size. 6.6.1.29 DIG_PATTERN_CHA_15:8 Register (Address = A3h) [Reset = 00h] Return to the Summary Table. Table 6-35. DIG_PATTERN_CHA_15:8 Register Field Descriptions Bit Field Type Reset Description 7:0 DIG_PATTERN_CHA__15 :8 R/W 0h Used with DIG PAT MODE CHA to set constant custom pattern starting from MSB or sets ramp pattern increment step size. 6.6.1.30 DIG_PATTERN_CHB_7:0 Register (Address = A4h) [Reset = 00h] Return to the Summary Table. Table 6-36. DIG_PATTERN_CHB_7:0 Register Field Descriptions Bit Field Type Reset Description 7:0 DIG_PATTERN_CHB__7: 0 R/W 0h Used with DIG PAT MODE CHB to set constant custom pattern starting from MSB or sets ramp pattern increment step size. 6.6.1.31 DIG_PATTERN_CHB_15:8 Register (Address = A5h) [Reset = 00h] Return to the Summary Table. Table 6-37. DIG_PATTERN_CHB_15:8 Register Field Descriptions Bit Field Type Reset Description 7:0 DIG_PATTERN_CHB__15 :8 R/W 0h Used with DIG PAT MODE CHB to set constant custom pattern starting from MSB or sets ramp pattern increment step size. 6.6.1.32 INTERFACE_CFG_4 Register (Address = A6h) [Reset = 00h] Return to the Summary Table. Table 6-38. INTERFACE_CFG_4 Register Field Descriptions Bit Field Type Reset Description 5 DDR_MODE R/W 0h Channel data output order. Applicable in DDR interface mode. 0b = Channel A data on rising edge and channel B on falling edge of DCLK 1b = Channel A data outputed first then channel B data 4:1 SERIALIZATION R/W 0h Serialization Factor 0000b = Parellel output 0001b = 2x serialization 0010b = 4x serialization 0011b = 8x serialization 0100b = 16x serialization 0 DIG_PAT_EN R/W 0h Enables the test patterns set in DIG PAT MODE CHA and DIG PAT MODE CHB. 0b = Normal output mode (test pattern disabled) 1b = Test pattern enabled www.ti.com ADC3910D125 SBASAD1 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 63 Product Folder Links: ADC3910D125 |
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