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ADC3908CSSS 数据表(PDF) 75 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 75 Page - Texas Instruments |
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75 / 131 page  6.6.1.74 CLK_TIM_ADJ_CHA Register (Address = 304h) [Reset = 00h] Return to the Summary Table. Table 6-80. CLK_TIM_ADJ_CHA Register Field Descriptions Bit Field Type Reset Description 7:1 CLK_TIM_ADJ_CHA R/W 0h ADC channel A sampling edge adjustment. Used in interleaved mode to reduce interleaving spur. Min. step size is 1 ps and adjustment range is 15 ps. 0 RESERVED R 0h 6.6.1.75 CLK_TIM_ADJ_CHB Register (Address = 305h) [Reset = 00h] Return to the Summary Table. Table 6-81. CLK_TIM_ADJ_CHB Register Field Descriptions Bit Field Type Reset Description 7 DCLK_OUT R/W 0h DCLK output disable 0b = DCLK output enabled 1b = DCLK output disabled 6:0 CLK_TIM_ADJ_CHB R/W 0h ADC channel B sampling edge adjustment. Used in interleaved mode to reduce interleaving spur. Min. step size is 1 ps and adjustment range is 15 ps. 6.6.1.76 DCLK_DLL_PD Register (Address = 306h) [Reset = 0h] Return to the Summary Table. Table 6-82. DCLK_DLL_PD Register Field Descriptions Bit Field Type Reset Description 0 DCLKDLL_PD R/W 0h DCLK DLL power down and bypass. Useful in SDR interface mode and reduces current by 1 mA. 0b = DCLK DLL enabled 1b = DCLK DLL power down and bypassed 6.6.1.77 DIG_INPUT_CFG Register (Address = 307h) [Reset = 00h] Return to the Summary Table. Table 6-83. DIG_INPUT_CFG Register Field Descriptions Bit Field Type Reset Description 4 DCLKZ_OUT R/W 0h DCLKZ output disable 0b = DCLKZ output enabled 1b = DCLKZ output disabled 3 DIG_INPUT R/W 0h Disables data inputs to digital block. 0b = Data inputs enabled to digital blocks 1b = Data input disabled to digital blocks 2:0 RESERVED R 0h 6.6.1.78 BUF_VCM_CURR Register (Address = 309h) [Reset = 00h] Return to the Summary Table. www.ti.com ADC3910D125 SBASAD1 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 75 Product Folder Links: ADC3910D125 |
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