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ADC3908CSSS 数据表(PDF) 68 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 68 Page - Texas Instruments |
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68 / 131 page  Table 6-46. OUTPUT_BIT_MAPPER_D10_D11 Register Field Descriptions (continued) Bit Field Type Reset Description 3:0 OUTPUT_BIT_MAPPER_ D10 R/W 3h These registers are used to reorder the output data bus. See the Output Bit Mapper on how to program. 0100b = Lane 0 (LSB) 0101b = Lane 1 0110b = Lane 2 0111b = Lane 3 1000b = Lane 4 1001b = Lane 5 1010b = Lane 6 1011b = Lane 7 1100b = Lane 8 1101b = Lane 9 1110b = Lane 10 1111b = Lane 11 (MSB) 6.6.1.41 ROUND Register (Address = B6h) [Reset = 00h] Return to the Summary Table. Table 6-47. ROUND Register Field Descriptions Bit Field Type Reset Description 4 ROUND R/W 0h The device uses a 16-bit resolution internally which can be useful for high decimation settings so that the quantization noise doesn't impact the ADC performance. 0b = Truncate 4 LSBs to reduce resolution from 16 bits to resolution specified in OUTPUT DATA WIDTH 1b = Round to reduce resolution from 16 bits to resolution specified in OUTPUT DATA WIDTH 3:0 RESERVED R 0h 6.6.1.42 COMP_THRESHOLD_HI_CHA_7:0 Register (Address = C8h) [Reset = 00h] Return to the Summary Table. Table 6-48. COMP_THRESHOLD_HI_CHA_7:0 Register Field Descriptions Bit Field Type Reset Description 7:0 COMP_THRESHOLD_HI_ CHA__7:0 R/W 0h Comparator high threshold for channel A 6.6.1.43 COMP_THRESHOLD_HI_CHA_11:8 Register (Address = C9h) [Reset = 0h] Return to the Summary Table. Table 6-49. COMP_THRESHOLD_HI_CHA_11:8 Register Field Descriptions Bit Field Type Reset Description 3:0 COMP_THRESHOLD_HI_ CHA__11:8 R/W 0h Comparator high threshold for channel A 6.6.1.44 COMP_THRESHOLD_HI_CHB_7:0 Register (Address = CAh) [Reset = 00h] Return to the Summary Table. ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 68 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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