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ADC3908CSSS 数据表(PDF) 60 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 60 Page - Texas Instruments |
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60 / 131 page  Table 6-24. TEST_PATTERN_CHB_7:0 Register Field Descriptions Bit Field Type Reset Description 7:0 TEST_PATTERN_CHB__ 7:0 R/W 0h 6.6.1.19 TEST_PATTERN_CHB_13:8 Register (Address = 93h) [Reset = 00h] Return to the Summary Table. Table 6-25. TEST_PATTERN_CHB_13:8 Register Field Descriptions Bit Field Type Reset Description 5:0 TEST_PATTERN_CHB__ 13:8 R/W 0h 6.6.1.20 TEST_PATTERN_CHA_7:0 Register (Address = 94h) [Reset = 00h] Return to the Summary Table. Table 6-26. TEST_PATTERN_CHA_7:0 Register Field Descriptions Bit Field Type Reset Description 7:0 TEST_PATTERN_CHA__ 7:0 R/W 0h 6.6.1.21 TEST_PATTERN_CHA_13:8 Register (Address = 95h) [Reset = 00h] Return to the Summary Table. Table 6-27. TEST_PATTERN_CHA_13:8 Register Field Descriptions Bit Field Type Reset Description 5:0 TEST_PATTERN_CHA__ 13:8 R/W 0h 6.6.1.22 GLOBAL_PDN Register (Address = 97h) [Reset = 00h] Return to the Summary Table. Table 6-28. GLOBAL_PDN Register Field Descriptions Bit Field Type Reset Description 5 PDN R/W 0h Global power down via SPI. 0b = Global power down disabled 1b = Global power down enabled. 4:0 RESERVED R 0h 6.6.1.23 INTERFACE_CFG_1 Register (Address = 98h) [Reset = 00h] Return to the Summary Table. Table 6-29. INTERFACE_CFG_1 Register Field Descriptions Bit Field Type Reset Description 7 OENZ_PDN R/W 0h Overwrites OENZ control pin as either global or fast power down 0b = OENZ control pin functions as output enable 1b = OENZ control pin functions as power down. Power down options in register 0x009C determine the power down mode. 6 RESERVED R 0h ADC3910D125 SBASAD1 – DECEMBER 2023 www.ti.com 60 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: ADC3910D125 |
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