ADC3908CSSS datasheet(116/131 Pages) TI1

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SFDR performance is a key care about as well. A higher ADC sampling rate is desirable to relax the external

anti-aliasing filter. An internal decimation filter can be used to reduce the digital output rate afterwards.

Table 7-1. Design key care-abouts

FEATURE

DESCRIPTION

Signal Bandwidth

DC to 30 MHz

Input Driver

Single ended to differential signal conversion and DC coupling

Clock Source

External clock with low jitter

When designing the amplifier/filter driving circuit, the ADC input full-scale voltage needs to be taken into

consideration. For example, the ADC3910D125 input full-scale is 1.9 VPP. When factoring in approximately 1

dB for insertion loss of the filter, then the amplifier needs to deliver close to 2.1 VPP. The amplifier distortion

performance degrades with a larger output swing and considering the ADC common mode input voltage the

amplifier may not be able to deliver the full swing. The ADC3910D125 provides an output common mode voltage

of 1.25 V and the THS4541 for example can only swing within 250 mV of its negative supply. A unipolar 3.3

V amplifier power supply limits the maximum voltage swing to approximately 2.8 VPP. Hence, if a larger output

swing is required (factoring in filter insertion loss) then a negative supply for the amplifier is needed in order to

eliminate that limitation. Additionally, input voltage protection diodes may be needed to protect the ADC from

over-voltage events.

Table 7-2. Output voltage swing of THS4541 vs power supply

DEVICE

MIN OUTPUT VOLTAGE

MAX SWING WITH 3.3 V/ 0 V SUPPLY

THS4541

VS- + 250 mV

2.8 VPP

7.2.2 Detailed Design Procedure

7.2.2.1 Input Signal Path

The THS4541 provides a good low power option to drive the ADC inputs. Table 7-3 provides an overview of the

THS4541 with power consumption and usable frequency.

Table 7-3. Fully Differential Amplifier Options

DEVICE

CURRENT (IQ) PER CHANNEL

USABLE FREQUENCY RANGE

THS4541

10 mA

< 70 MHz

The low pass filter design (topology, filter order) is driven by the application itself. However, when designing the

low pass filter, the optimum load impedance for the amplifier must also be taken into consideration.

7.2.2.2 Sampling Clock

Applications operating with low input frequencies (such as DC to 20 MHz) typically are less sensitive to

performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall

times (that is, square wave vs sine wave).

Termination of the clock input needs to be considered for long clock traces.

7.2.2.3 Voltage Reference

The ADC3910D125 provides two different options for supplying the voltage reference to the ADC. An external

1.2 V reference can be directly connected to the VREF input or the internal 1.2 V reference can be enabled to

generate a reference voltage. For best performance, the reference noise needs to be filtered by connecting a

10 uF and a 0.1 uF ceramic bypass capacitor to the VREF pin when using an external reference and can be

connected to ground when the internal reference is used.

Note

The voltage reference mode can be selected using SPI writes.

ADC3910D125

SBASAD1 – DECEMBER 2023

www.ti.com

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