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ADC3908CSSS 数据表(PDF) 121 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 121 Page - Texas Instruments |
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121 / 131 page ![]() 7.5.2 Layout Example The following screen shot shows the top layer of the ADC3910D125EVM. • Signal inputs are routed as different signal and along with clock input on the top layer avoiding vias. • Serial CMOS output interface lanes with isolation resistor. • Bypass caps are close to the VREF pin on the top layer avoiding vias. Clock routing without vias Analog inputs routed on top layer with no vias CMOS output lines with isolation resistors Bypass caps close to VREF pin Figure 7-7. Layout Example: top layer of ADC3910D125EVM www.ti.com ADC3910D125 SBASAD1 – DECEMBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 121 Product Folder Links: ADC3910D125 |
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