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TDA4VEN...Q1 数据表(PDF) 178 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 178 Page - Texas Instruments |
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178 / 236 page  6.9.5.18.1.1 Legacy SDR Mode Table 6-83, Figure 6-68, Table 6-84, and Figure 6-69 present timing requirements and switching characteristics for MMC0 – Legacy SDR Mode. Table 6-83. MMC0 Timing Requirements – Legacy SDR Mode see Figure 6-68 NO. IO Operating Voltage MIN MAX UNIT LSDR1 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 1.8V 4.2 ns 3.3V 2.15 ns LSDR2 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 1.8V 0.87 ns 3.3V 1.67 ns LSDR3 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge 1.8V 4.2 ns 3.3V 2.15 ns LSDR4 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge 1.8V 0.87 ns 3.3V 1.67 ns Figure 6-68. MMC0 – Legacy SDR – Receive Mode Table 6-84. MMC0 Switching Characteristics – Legacy SDR Mode see Figure 6-69 NO. PARAMETER IO Operating Voltage MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 25 MHz LSDR5 tc(clk) Cycle time, MMC0_CLK 40 ns LSDR6 tw(clkH) Pulse duration, MMC0_CLK high 18.7 ns LSDR7 tw(clkL) Pulse duration, MMC0_CLK low 18.7 ns LSDR8 td(clkL-cmdV) Delay time, MMC0_CLK falling edge to MMC0_CMD transition 1.8V -2.1 2.1 ns 3.3V -1.8 2.2 ns LSDR9 td(clkL-dV) Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition 1.8V -2.1 2.1 ns 3.3V -1.8 2.2 ns Figure 6-69. MMC0 – Legacy SDR – Transmit Mode TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 178 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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