TDA4VEN...Q1 datasheet(180/236 Pages) TI

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6.9.5.18.1.3 High Speed DDR Mode

Table 6-87, Figure 6-72, Table 6-88, and Figure 6-73 present timing requirements and switching characteristics

for MMC0 – High Speed DDR Mode.

Table 6-87. MMC0 Timing Requirements – High Speed DDR Mode

see Figure 6-72

NO.

MIN

MAX

UNIT

HSDDR1

tsu(cmdV-clk)

Setup time, MMC0_CMD valid before MMC0_CLK rising edge

1.62

HSDDR2

th(clk-cmdV)

Hold time, MMC0_CMD valid after MMC0_CLK rising edge

2.52

HSDDR3

tsu(dV-clk)

Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition

0.83

HSDDR4

th(clk-dV)

Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition

1.76

Figure 6-72. MMC0 – High Speed DDR Mode – Receive Mode

Table 6-88. MMC0 Switching Characteristics – High Speed DDR Mode

see Figure 6-73

NO.

PARAMETER

MIN

MAX

UNIT

fop(clk)

Operating frequency, MMC0_CLK

MHz

HSDDR5

tc(clk)

Cycle time, MMC0_CLK

HSDDR6

tw(clkH)

Pulse duration, MMC0_CLK high

9.2

HSDDR7

tw(clkL)

Pulse duration, MMC0_CLK low

9.2

HSDDR8

td(clk-cmdV)

Delay time, MMC0_CLK rising edge to MMC0_CMD transition

3.31

7.65

HSDDR9

td(clk-dV)

Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition

2.81

6.94

Figure 6-73. MMC0 – High Speed DDR Mode – Transmit Mode

TDA4VEN-Q1, TDA4AEN-Q1

SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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