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TDA4VEN...Q1 数据表(PDF) 184 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 184 Page - Texas Instruments |
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184 / 236 page  6.9.5.18.1.6 UHS–I SDR12 Mode Table 6-92, Figure 6-77, Table 6-93, and Figure 6-78 present timing requirements and switching characteristics for MMC0 – UHS-I SDR12 Mode. Table 6-92. Timing Requirements for MMC0 – UHS-I SDR12 Mode see Figure 6-77 NO. MIN MAX UNIT SDR121 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 4.2 ns SDR122 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 0.87 ns SDR123 tsu(dV-clkH) Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge 4.2 ns SDR124 th(clkH-dV) Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge 0.87 ns MMC[ ]_CMD x MMC DAT [ ]_ [3:0] x SDR121 SDR122 SDR123 SDR124 MMC[ ]_CLK x Figure 6-77. MMC0 – UHS-I SDR12 – Receive Mode Table 6-93. Switching Characteristics for MMC0 – UHS-I SDR12 Mode see Figure 6-78 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMC0_CLK 25 MHz SDR125 tc(clk) Cycle time, MMC0_CLK 40 ns SDR126 tw(clkH) Pulse duration, MMC0_CLK high 18.7 ns SDR127 tw(clkL) Pulse duration, MMC0_CLK low 18.7 ns SDR128 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 1.5 8.6 ns SDR129 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition 1.5 8.6 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ ]_ [3:0] x SDR125 SDR127 SDR126 SDR128 SDR129 SDR128 SDR129 Figure 6-78. MMC0 – UHS-I SDR12 – Transmit Mode TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com 184 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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