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TDA4VEN...Q1 数据表(PDF) 191 Page - Texas Instruments |
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TDA4VEN...Q1 数据表(HTML) 191 Page - Texas Instruments |
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191 / 236 page  6.9.5.18.2.1 Default Speed Mode Table 6-101, Figure 6-84, Table 6-102, and Figure 6-85 present timing requirements and switching characteristics for MMC1/MMC2 – Default Speed Mode. Table 6-101. Timing Requirements for MMC1/MMC2 – Default Speed Mode see Figure 6-84 NO. MIN MAX UNIT DS1 tsu(cmdV-clkH) Setup time, MMCx_CMD valid before MMCx_CLK rising edge 2.15 ns DS2 th(clkH-cmdV) Hold time, MMCx_CMD valid after MMCx_CLK rising edge 1.67 ns DS3 tsu(dV-clkH) Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge 2.15 ns DS4 th(clkH-dV) Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge 1.67 ns MMC[ ]_CLK x M [ ]_ MC CMD x MMC DAT [ ]_ [3:0] x DS1 DS2 DS3 DS4 Figure 6-84. MMC1/MMC2 – Default Speed – Receive Mode Table 6-102. Switching Characteristics for MMC1/MMC2 – Default Speed Mode see Figure 6-85 NO. PARAMETER MIN MAX UNIT fop(clk) Operating frequency, MMCx_CLK 25 MHz DS5 tc(clk) Cycle time, MMCx_CLK 40 ns DS6 tw(clkH) Pulse duration, MMCx_CLK high 18.7 ns DS7 tw(clkL) Pulse duration, MMCx_CLK low 18.7 ns DS8 td(clkL-cmdV) Delay time, MMCx_CLK falling edge to MMCx_CMD transition - 1.8 2.2 ns DS9 td(clkL-dV) Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition - 1.8 2.2 ns MMC[ ]_CLK x MMC CMD [ ]_ x MMC DAT [ _ [3:0] x] D 5 S D 7 S D 8 S D 9 S DS6 Figure 6-85. MMC1/MMC2 – Default Speed – Transmit Mode www.ti.com TDA4VEN-Q1, TDA4AEN-Q1 SPRSP96A – MARCH 2024 – REVISED SEPTEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 191 Product Folder Links: TDA4VEN-Q1 TDA4AEN-Q1 |
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