TMP86FS49AIUG datasheet(125/296 Pages) TOSHIBA

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Page 109

TMP86FS49AIUG

10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4)

This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The

up-counter counts up using the internal clock.

When a match between the up-counter and the PWREGj value is detected, the logic level output from the

timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the

timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The

INTTCj interrupt request is generated at this time.

Since the initial value can be set to the timer F/Fj by TCjCR<TFFj>, positive and negative pulses can be gen-

erated. Upon reset, the timer F/Fj is cleared to 0.

(The logic level output from the PWMj pin is the opposite to the timer F/Fj logic level.)

Since PWREGj in the PWM mode is serially connected to the shift register, the value set to PWREGj can be

changed while the timer is running. The value set to PWREGj during a run of the timer is shifted by the

INTTCj interrupt request and loaded into PWREGj. While the timer is stopped, the value is shifted immedi-

ately after the programming of PWREGj. If executing the read instruction to PWREGj during PWM output,

the value in the shift register is read, but not the value set in PWREGj. Therefore, after writing to PWREGj, the

reading data of PWREGj is previous value until INTTCj is generated.

For the pin used for PWM output, the output latch of the I/O port must be set to 1.

Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is

generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the inter-

rupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse

different from the programmed value until the next INTTCj interrupt request is generated.

Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is

stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the

TCjCR<TFFj> upon stopping of the timer.

Example: Fixing the PWMj pin to the high level when the TimerCounter is stopped

CLR (TCjCR).3: Stops the timer.

CLR (TCjCR).7: Sets the PWMj pin to the high level.

Note 3: To enter the STOP mode during PWM output, stop the timer and then enter the STOP mode. If the STOP

mode is entered without stopping the timer when fc, fc/2 or fs is selected as the source clock, a pulse is out-

put from the PWMj pin during the warm-up period time after exiting the STOP mode.

Note 4: j = 3, 4

Table 10-5 PWM Output Mode

Source Clock

Resolution

Repeated Cycle

NORMAL1/2, IDLE1/2 mode

SLOW1/2,

SLEEP1/2

mode

fc = 16 MHz

fs = 32.768 kHz

fc = 16 MHz

fs = 32.768 kHz

DV7CK = 0

DV7CK = 1

fc/211 [Hz]

fs/23 [Hz]

128

µs244.14 µs

32.8 ms

62.5 ms

fc/27

–8

µs–

2.05 ms

–

fc/25

–2

µs

–

512

µs–

fc/23

–

500 ns

–

128

µs–

30.5

µs30.5 µs

7.81 ms

fc/2

–

125 ns

–

µs–

–

62.5 ns

–

µs–

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