TMP86FS49AIUG datasheet(128/296 Pages) TOSHIBA

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10. 8-Bit TimerCounter (TC3, TC4)

10.1 Configuration

TMP86FS49AIUG

10.3.6 16-Bit Event Counter Mode (TC3 and 4)

10.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4)

This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The

TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator.

The counter counts up using the internal clock or external clock.

When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the

logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The

logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the

counter is cleared. The INTTC4 interrupt is generated at this time.

Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maxi-

mum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or

SLEEP1/2 mode.

Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be

generated. Upon reset, the timer F/F4 is cleared to 0.

(The logic level output from the PWM4 pin is the opposite to the timer F/F4 logic level.)

Since PWREG4 and 3 in the PWM mode are serially connected to the shift register, the values set to

PWREG4 and 3 can be changed while the timer is running. The values set to PWREG4 and 3 during a run of

the timer are shifted by the INTTCj interrupt request and loaded into PWREG4 and 3. While the timer is

stopped, the values are shifted immediately after the programming of PWREG4 and 3. Set the lower byte

(PWREG3) and upper byte (PWREG3) in this order to program PWREG4 and 3. (Programming only the lower

or upper byte of the register should not be attempted.)

If executing the read instruction to PWREG4 and 3 during PWM output, the values set in the shift register is

read, but not the values set in PWREG4 and 3. Therefore, after writing to the PWREG4 and 3, reading data of

PWREG4 and 3 is previous value until INTTC4 is generated.

For the pin used for PWM output, the output latch of the I/O port must be set to 1.

Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt

request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and

the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of

pulse different from the programmed value until the next INTTC4 interrupt request is generated.

Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is

stopped. To change the output status, program TC4CR<TFF4> after the timer is stopped. Do not program

TC4CR<TFF4> upon stopping of the timer.

Example: Fixing thePWM4 pin to the high level when the TimerCounter is stopped

In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3

and 4 are cascadable to form a 16-bit event counter.

When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after

the timer is started by setting TC4CR<TC4S> to 1, an INTTC4 interrupt is generated and the up-counter is

cleared.

After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TC3 pin.

Two machine cycles are required for the low- or high-level pulse input to the TC3 pin.

Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 in

the SLOW1/2 or SLEEP1/2 mode. Program the lower byte (TTREG3), and upper byte (TTREG4) in this

order in the timer register. (Programming only the upper or lower byte should not be attempted.)

Note 1:

Note 2:

Note 3:

In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output pulses.

In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in

the shift register configuration in the event counter mode, the new value programmed in TTREGj is in effect imme-

diately after the programming. Therefore, if TTREGj is changed while the timer is running, an expected operation

may not be obtained.

j = 3, 4

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