TMP86FS49AIUG datasheet(129/296 Pages) TOSHIBA

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Page 113

TMP86FS49AIUG

CLR (TC4CR).3: Stops the timer.

CLR (TC4CR).7 : Sets the PWM4 pin to the high level.

Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with-

out stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4

pin during the warm-up period time after exiting the STOP mode.

Table 10-7 16-Bit PWM Output Mode

Source Clock

Resolution

Repeated Cycle

NORMAL1/2, IDLE1/2 mode

SLOW1/2,

SLEEP1/2

mode

fc = 16 MHz

fs = 32.768 kHz

fc = 16 MHz

fs = 32.768 kHz

DV7CK = 0

DV7CK = 1

fc/211

fs/23 [Hz]

128

µs244.14 µs

8.39 s

16 s

fc/27

–8

µs

–

524.3 ms

–

fc/25

–2

µs

–

131.1 ms

–

fc/23

–

500ns

–

32.8 ms

–

30.5

µs30.5 µs2 s

2 s

fc/2

–

125 ns

–

8.2 ms

–

62.5 ns

–

4.1 ms

–

Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz)

Setting ports

LDW

(PWREG3), 07D0H

: Sets the pulse width.

(TC3CR), 33H

: Sets the operating clock to fc/23, and 16-bit PWM output

mode (lower byte).

(TC4CR), 056H

: Sets TFF4 to the initial value 0, and 16-bit PWM signal

generation mode (upper byte).

(TC4CR), 05EH

: Starts the timer.

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