TMP86FS49AIUG datasheet(161/296 Pages) TOSHIBA

161 / 296 page

Page 145

TMP86FS49AIUG

12.9 Status Flag

12.9.1 Parity Error

When parity determined using the receive data bits differs from the received parity bit, the parity error flag

UART1SR<PERR> is set to “1”. The UART1SR<PERR> is cleared to “0” when the RD1BUF is read after

reading the UART1SR.

Figure 12-5 Generation of Parity Error

12.9.2 Framing Error

When “0” is sampled as the stop bit in the receive data, framing error flag UART1SR<FERR> is set to “1”.

The UART1SR<FERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR.

Figure 12-6 Generation of Framing Error

12.9.3 Overrun Error

When all bits in the next data are received while unread data are still in RD1BUF, overrun error flag

UART1SR<OERR> is set to “1”. In this case, the receive data is discarded; data in RD1BUF are not affected.

The UART1SR<OERR> is cleared to “0” when the RD1BUF is read after reading the UART1SR.

Parity

Stop

Shift register

pxxxx0*

1pxxxx0

xxxx0**

RXD1 pin

UART1SR<PERR>

INTRXD1 interrupt

After reading UART1SR then

RD1BUF clears PERR.

Final bit

Stop

Shift register

xxxx0*

0xxxx0

xxx0**

RXD1 pin

UART1SR<FERR>

INTRXD1 interrupt

After reading UART1SR then

RD1BUF clears FERR.

TMP86FS49AIUG 数据表(PDF) 161 Page - Toshiba Semiconductor

TMP86FS49AIUG 数据表(HTML) 161 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载