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TMP86FS49AIUG 数据表(PDF) 165 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 165 Page - Toshiba Semiconductor |
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165 / 296 page ![]() Page 149 TMP86FS49AIUG 13. Asynchronous Serial interface (UART2 ) 13.1 Configuration Figure 13-1 UART2 (Asynchronous Serial Interface) Counter Y A B C S S A B C D Y E F G H UART status register UART control register 2 UART control register 1 Transmit data buffer Receive data buffer fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 fc/96 Stop bit Parity bit fc/2 6 fc/2 7 fc/2 8 Baud rate generator Transmit/receive clock 2 4 3 2 2 2 Noise rejection circuit M P X Shift register Shift register MPX: Multiplexer UART2CR1 TD2BUF RD2BUF INTTXD2 INTRXD2 UART2SR UART2CR2 RXD2 TXD2 INTTC5 |
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