TMP86FS49AIUG datasheet(166/296 Pages) TOSHIBA

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Page 150

13. Asynchronous Serial interface (UART2 )

13.2 Control

TMP86FS49AIUG

13.2 Control

UART2 is controlled by the UART2 Control Registers (UART2CR1, UART2CR2). The operating status can be

monitored using the UART status register (UART2SR).

Note 1: When operations are disabled by setting TXE and RXE bit to “0”, the setting becomes valid when data transmit or receive

complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit

is enabled, until new data are written to the transmit data buffer, the current data are not transmitted.

Note 2: The transmit clock and the parity are common to transmit and receive.

Note 3: UART2CR1<RXE> and UART2CR1<TXE> should be set to “0” before UART2CR1<BRG> is changed.

Note: When

UART2CR2<RXDNC> = “01”, pulses longer than 96/fc [s] are always regarded

signals; when

UART2CR2<RXDNC> = “10”, longer than 192/fc [s]; and when UART2CR2<RXDNC> = “11”, longer than 384/fc [s].

UART2 Control Register1

UART2CR1

(0F98H)

543

210

TXE

RXE

STBT

EVEN

BRG

(Initial value: 0000 0000)

TXE

Transfer operation

Disable

Enable

Write

only

RXE

Receive operation

Disable

Enable

STBT

Transmit stop bit length

1 bit

2 bits

EVEN

Even-numbered parity

Odd-numbered parity

Even-numbered parity

Parity addition

No parity

Parity

BRG

Transmit clock select

000:

001:

010:

011:

100:

101:

110:

111:

fc/13 [Hz]

fc/26

fc/52

fc/104

fc/208

fc/416

TC5 ( Input INTTC5)

fc/96

UART2 Control Register2

UART2CR2

(0F99H)

765

432

RXDNC

STOPBR

(Initial value: **** *000)

RXDNC

Selection of RXD input noise

rejectio time

00:

01:

10:

11:

No noise rejection (Hysteresis input)

Rejects pulses shorter than 31/fc [s] as noise

Rejects pulses shorter than 63/fc [s] as noise

Rejects pulses shorter than 127/fc [s] as noise

Write

only

STOPBR

Receive stop bit length

1 bit

2 bits

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