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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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TMP86FS49AIUG 数据表(PDF) 245 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 数据表(HTML) 245 Page - Toshiba Semiconductor |
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245 / 296 page  Page 229 TMP86FS49AIUG Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H. DI : Disable interrupts (IMF ←"0") LD (FLSCR),0011_1000B : Enable command sequence execution. LD IX,0F555H LD IY,0FAAAH LD HL,0F000H ; #### Flash Memory Chip erase Process #### LD (IX),0AAH : 1st bus write cycle LD (IY),55H : 2nd bus write cycle LD (IX),80H : 3rd bus write cycle LD (IX),0AAH : 4th bus write cycle LD (IY),55H : 5th bus write cycle LD (IX),10H : 6th bus write cycle sLOOP1: LD W,(IX) CMP W,(IX) JR NZ,sLOOP1 : Loop until the same value is read. SET (FLSCR).3 : Set BANK1. ; #### Flash Memory Write Process #### LD (IX),0AAH : 1st bus write cycle LD (IY),55H : 2nd bus write cycle LD (IX),0A0H : 3rd bus write cycle LD (HL),3FH : 4th bus write cycle, (F000H)=3FH sLOOP2: LD W,(HL) CMP W,(HL) JR NZ,sLOOP2 : Loop until the same value is read. LD (FLSCR),1100_1000B : Disable command sequence execution. sLOOP3: JP sLOOP3 |
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