TMP86FS49AIUG datasheet(258/296 Pages) TOSHIBA

258 / 296 page

Page 242

20. Serial PROM Mode

20.6 Operation Mode

TMP86FS49AIUG

2. The 5th byte of the received data contains the command data in the flash memory erasing mode

(F0H).

3. When the 5th byte of the received data contains the operation command data shown in Table 20-6, the

device echoes back the value which is the same data in the 6th byte position of the received data (in

this case, F0H). If the 5th byte of the received data does not contain the operation command data, the

device enters the halt condition after sending 3 bytes of the operation command error code (63H).

4. The 7th thorough m'th bytes of the transmitted and received data contain the same data as in the flash

memory writing mode. In the case of a blank product, do not transmit a password string. (Do not

transmit a dummy password string.)

5. The n’th - 2 byte contains the erasure area specification data. The upper 4 bits and lower 4 bits specify

the start address and end address of the erasure area, respectively. For the detailed description, see

“1.13 Specifying the Erasure Area”.

6. The n’th - 1 byte and n’th byte contain the upper and lower bytes of the checksum, respectively. For

how to calculate the checksum, refer to “1.8 Checksum (SUM)”. Checksum is calculated unless a

receiving error or Intel Hex format error occurs. After sending the end record, the external controller

judges whether the transmission is completed correctly by receiving the checksum sent by the device.

7. After sending the checksum, the device waits for the next operation command data.

TMP86FS49AIUG 数据表(PDF) 258 Page - Toshiba Semiconductor