TMP86FS49AIUG datasheet(263/296 Pages) TOSHIBA

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Page 247

TMP86FS49AIUG

Note 8: If an error occurs during the reception of a password address or a password string, TMP86FS49AIUG stops UART com-

munication and enters the halt condition. In this case, initialize TMP86FS49AIUG by the RESET pin and reactivate the

serial PROM mode.

Description of RAM loader mode

1. The 1st through 4th bytes of the transmitted and received data contains the same data as in the flash

memory writing mode.

2. In the 5th byte of the received data contains the RAM loader command data (60H).

3. When th 5th byte of the received data contains the operation command data shown in Table 1-6, the

device echoes back the value which is the same data in the 6th byte position (in this case, 60H). If the

5th byte does not contain the operation command data, the device enters the halt condition after send-

ing 3 bytes of operation command error code (63H).

4. The 7th through m’th bytes of the transmitted and received data contain the same data as in the flash

memory writing mode.

5. The m’th + 1 through n’th - 2 bytes of the received data contain the binary data in the Intel Hex for-

mat. No received data is echoed back to the external controller. After receiving the start mark (3AH

for “:”) in the Intel Hex format, the device starts data record reception. Therefore, the received data

except 3AH is ignored until the start mark is received. After receiving the start mark, the device

receives the data record, that consists of data length, address, record type, write data and checksum.

The writing data of the data record is written into RAM specified by address. Since the device starts

checksum calculation after receiving an end record, the external controller should wait for the check-

sum after sending the end record. If a receiving error or Intel Hex format error occurs, the device

enters the halts condition without returning an error code to the external controller.

6. The n’th - 1 and n’th bytes contain the checksum upper and lower bytes. For details on how to calcu-

late the SUM, refer to " 20.8 Checksum (SUM) ". The checksum is calculated only when the end

record is detected and no receiving error or Intel Hex format error occurs. After sending the end

record, the external controller judges whether the transmission is completed correctly by receiving the

checksum sent by the device.

7. After transmitting the checksum to the external controller, the boot program jumps to the RAM

address that is specified by the first received data record.

Note 1: To rewrite data to Flash memory addresses at which data (including FFH) is already written, make sure to

erase the existing data by "sector erase" or "chip erase" before rewriting data.

TMP86FS49AIUG 数据表(PDF) 263 Page - Toshiba Semiconductor