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MSC8103/D 数据表(PDF) 22 Page - Freescale Semiconductor, Inc |
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MSC8103/D 数据表(HTML) 22 Page - Freescale Semiconductor, Inc |
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22 / 104 page  MSC8103 Network Digital Signal Processor, Rev. 11 1-18 Freescale Semiconductor Signals/Connections PA22 FCC1: TXD3 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 3 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 3 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. PA21 FCC1: TXD4 UTOPIA FCC1: TXD3 MII and HDLC nibble Output Output FCC1: UTOPIA Transmit Data Bit 4 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 4 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 3 TXD[3–0] supports MII and HDLC nibble modes in FCC1. TXD3 is the most significant bit. PA20 FCC1: TXD5 UTOPIA FCC1: TXD2 MII and HDLC nibble Output Output FCC1: UTOPIA Transmit Data Bit 5 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 5 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 2 TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. This is bit 2 of the transmit data. TXD3 is the most significant bit. PA19 FCC1: TXD6 UTOPIA FCC1: TXD1 MII and HDLC nibble Output Output FCC1: UTOPIA Transmit Data Bit 6 The MSC8103MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 6 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 1 TXD[3–0] is supported by MII and HDLC transparent nibble modes in FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit. PA18 FCC1: TXD7 UTOPIA FCC1: TXD0 MII and HDLC nibble FCC1: TXD HDLC serial and transparent Output Output Output FCC1: UTOPIA Transmit Data Bit 7. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: MII and HDLC Nibble Transmit Data Bit 0 TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. TXD0 is the least significant bit. FCC1: HDLC Serial and Transparent Transmit Data Bit This is the single transmit data bit in supported by HDLC serial and transparent modes. Table 1-7. Port A Signals (Continued) Name Dedicated I/O Data Direction Description General- Purpose I/O Peripheral Controller: Dedicated Signal Protocol |
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