MSC8103SLASHD datasheet(14/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

1-10

Freescale Semiconductor

Signals/Connections

D56

HACK/HACK

HRRQ/HRRQ

Input/Output

Output

Data Bus Bit 56

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Acknowledge3

When the HDI16 is programmed to interface with a single host request host bus, this pin is the host

acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable.

Receive Host Request3

When the HDI16 is programmed to interface with a double host request host bus, this pin is the

receive host request output (HRRQ/HRRQ). The signal can be programmed as driven or open drain.

The polarity of the host request is programmable.

D57

HDSP

Input/Output

Input

Data Bus Bit 57

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Data Strobe Polarity3

When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP).

D58

HDDS

Input/Output

Input

Data Bus Bit 58

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Dual Data Strobe3

When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS).

D59

H8BIT

Input/Output

Input

Data Bus Bit 59

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

H8BIT3

When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mode.

D60

HCS2

Input/Output

Input

Data Bus Bit 60

In write transactions the bus master drives the valid data on this pin. In read transactions the slave

drives the valid data on this pin.

Host Chip Select 3

When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select

is a logical OR of HCS1 and HCS2.

D[61–63]

Reserved

Input/Output

Data Bus Bits 61–63

Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this

bus. In read transactions the slave drives the valid data on this bus.

These dedicated signals are reserved when the HDI16 is enabled.3

Reserved

DP0

EXT_BR2

Input

Input/Output

Input

The primary configuration is reserved.

Data Parity 01

The agent that drives the data bus also drives the data parity signals. The value driven on the data

parity zero pin should give odd parity (odd number of ones) on the group of signals that includes

data parity 0 and D[0–7].

External Bus Request 21,2

An external master asserts this pin to request bus ownership from the internal arbiter.

Table 1-5.

System Bus, HDI16, and Interrupt Signals (Continued)

Signal

Data Flow

Description

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