MSC8103SLASHD datasheet(35/104 Pages) FREESCALE

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CPM Ports

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

1-31

PC7

SI2: L1ST1

FCC1: CTS

HDLC serial, HDLC nibble,

and

transparent

FCC1: TXADDR2

UTOPIA master

FCC1: TXADDR2

UTOPIA slave

FCC1: TXCLAV1

UTOPIA multi-PHY master, direct

polling

Output

Input

Output

Input

Serial Interface 2: Strobe 1

The MSC8103 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

FCC1: Clear To Send

In the standard modem interface signals supported by FCC1 (RTS, CTS,

and CD). CTS is asynchronous with the data.

FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2

This is master transmit address bit 2.

FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2

This is slave transmit address bit 2.

FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 1 Direct

Polling

Asserted by an external UTOPIA slave PHY to indicate that it can accept

one complete ATM cell.

PC6

SI2: L1ST2

FCC1: CD

HDLC serial, HDLC nibble,

and

transparent

FCC1: RXADDR2

UTOPIA master

FCC1: RXADDR2

UTOPIA slave

FCC1: RXCLAV1

UTOPIA multi-PHY master, direct

polling

Output

Input

Output

Input

Serial Interface 2: Layer 1 Strobe 2

The MSC8103 time-slot assigner supports up to four strobe outputs that

can be asserted on a bit or byte basis. The strobe outputs are useful for

interfacing to other devices that do not support the multiplexed interface or

for enabling/disabling three-state I/O buffers in a multiple-transmitter

architecture. These strobes can also generate output wave forms for such

applications as stepper-motor control.

FCC1: Carrier Detect

In the standard modem interface signals supported by FCC1 (RTS, CTS,

and CD). CD is an input asynchronous with the data.

FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2

This is master receive address bit 2.

FCC1: UTOPIA Slave Receive Address Bit 2

This is slave receive address bit 2.

FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct

Polling

Asserted by an external PHY when one complete ATM cell is available for

transfer.

Table 1-9.

Port C Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

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