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MSC8103/D 数据表(PDF) 59 Page - Freescale Semiconductor, Inc |
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MSC8103/D 数据表(HTML) 59 Page - Freescale Semiconductor, Inc |
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59 / 104 page  AC Timings MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor 2-19 Figure 2-12 and Figure 2-13 show HDI16 read signal timing. Figure 2-14 and Figure 2-15 show HDI16 write signal timing. 48 Host data input minimum hold time after write data strobe deassertion8 Host data input minimum hold time after HACK write deassertion — 5.0 ns 49 Read data strobe minimum assertion to output data active from high impedance4 HACK read minimum assertion to output data active from high impedance — 5.0 ns 50 Read data strobe maximum assertion to output data valid4 HACK read maximum assertion to output data valid (2.0 × TC) + 5.0 Note 11 ns 51 Read data strobe maximum deassertion to output data high impedance4 HACK read maximum deassertion to output data high impedance — 5.0 ns 52 Output data minimum hold time after read data strobe deassertion4 Output data minimum hold time after HACK read deassertion — 5.0 ns 53 HCS[1–2] minimum assertion to read data strobe assertion4 —5.0 ns 54 HCS[1–2] minimum assertion to write data strobe assertion8 —5.0 ns 55 HCS[1–2] maximum assertion to output data valid TC + 5.0 Note 11 ns 56 HCS[1–2] minimum hold time after data strobe deassertion9 —0.0 ns 57 HA[0–3], HRW minimum set-up time before data strobe assertion9 • Read •Write — 0 5.0 ns ns 58 HA[0–3], HRW minimum hold time after data strobe deassertion9 —5.0 ns 61 Maximum delay from read data strobe deassertion to host request deassertion for “Last Data Register” read4, 5, 10 (3.5 × TC) + 5.0 Note 11 ns 62 Maximum delay from write data strobe deassertion to host request deassertion for “Last Data Register” write5,8,10 (3.0 × TC) + 5 Note 11 ns 63 Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) deassertion to HREQ assertion. (5.0 × TC) + 5.0 Note 11 ns 64 Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) assertion to HREQ deassertion (3.5 × TC) + 5.0 Note 11 ns Notes: 1. TC = 1/ DSPCLK. At 300 MHz, TC = 3.3 ns 2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. 3. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF 4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode. 5. In 64-bit mode, The “last data register” is the register at address $7, which is the last location to be read or written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1). 6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe (HDS/HDS) in the single data strobe mode. 10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full (treat as level Host Request). 11. Compute the value using the expression. Table 2-19. Host Interface (HDI16) Timing1, 2 (Continued) Number Characteristics3 Expression Value Unit |
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