MSC8103SLASHD datasheet(65/104 Pages) FREESCALE

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AC Timings

MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

2-25

Note:

The timing values refer to minimum system timing requirements. Actual implementation requires

conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and

output signals associated with the referenced internal controllers and supported communication protocols.

For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling

mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of

signals; the direction (input or output) of some of the shared signal names depends on the selected mode.

2.6.8

JTAG Signals

Figure 2-23.

PIO, Timer, and DMA Signal Diagram

Table 2-22.

JTAG Timing

No.

Characteristics

All frequencies

Unit

Min

Max

500

TCK frequency of operation

0.0

40.0

MHz

501

TCK cycle time

25.0

—

502

TCK clock pulse width measured at 1.6 V

12.5

—

503

TCK rise and fall times

0.0

3.0

508

TMS, TDI data set-up time

6.0

—

509

TMS, TDI data hold time

3.0

—

510

TCK low to TDO data valid

0.0

15.0

511

TCK low to TDO high impedance

0.0

20.0

512

TRST assert time

100.0

—

513

TRST set-up time to TCK low

40.0

—

Figure 2-24.

Test Clock Input Timing Diagram

DLLIN

PIO/TIMER/DMA inputs

PIO/TIMER/DMA outputs

TCK

(Input)

VIH

VIL

501

502

503

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