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MSC8103/D 数据表(PDF) 63 Page - Freescale Semiconductor, Inc |
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MSC8103/D 数据表(HTML) 63 Page - Freescale Semiconductor, Inc |
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63 / 104 page  AC Timings MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor 2-23 2.6.7 CPM Timings Table 2-20. CPM Input Characteristics No. Characteristic Typical Unit 39 FCC input set-up time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 10 5 ns ns 17 FCC input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 0 3 ns ns 18 SCC/SMC/SPI/I2C input set-up time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 20 5 ns ns 19 SCC/SMC/SPI/I2C input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 0 5 ns ns 20 TDM input set-up time before low-to-high serial clock transition 5 ns 21 TDM input hold time after low-to-high serial transition 5 ns 22 PIO/TIMER/DMA input set-up time before low-to-high serial clock transition 10 ns 23 PIO/TIMER/DMA input hold time after low-to-high serial clock transition 3 ns Note: FCC, SCC, SMC, SPI, I2C are non-multiplexed serial interface signals. Table 2-21. CPM Output Characteristics No. Characteristic Min Max Unit 41 FCC output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) 0 2 6 18 ns ns 38 SCC/SMC/SPI/I2C output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) 0 0 20 30 ns ns 40 TDM output delay after low-to-high serial clock transition 5 15 ns 42 PIO/TIMER/DMA output delay after low-to-high serial clock transition 1 14 ns Note: FCC, SCC, SMC, SPI, I2C are Non-Multiplexed Serial Interface signals. Figure 2-18. FCC Internal Clock Diagram BRGxO FCC inputs FCC outputs 29a 17a 41a |
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