MSC8103SLASHD datasheet(12/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

1-8

Freescale Semiconductor

Signals/Connections

Input/Output

Output

Input

Bus Request2

An output when an external arbiter is used. The MSC8103 asserts this pin to request ownership of

the bus.

An input when an internal arbiter is used. An external master should assert this pin to request bus

ownership from the internal arbiter.

Input/Output

Output

Input

Bus Grant2

An output when an internal arbiter is used. The MSC8103 asserts this pin to grant bus ownership to

an external bus master.

An input when an external arbiter is used. The external arbiter should assert this pin to grant bus

ownership to the MSC8103.

ABB

IRQ2

Input/Output

Output

Input

Address Bus Busy1

The MSC8103 asserts this pin for the duration of the address bus tenure. Following an address

acknowledge (AACK) signal, which terminates the address bus tenure, the MSC8103 deasserts

ABB for a fraction of a bus cycle and then stops driving this pin.

The MSC8103 does not assume bus ownership while it this pin is asserted by an external bus

master.

Interrupt Request 21

One of the eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

Input/Output

Bus Transfer Start

Signals the beginning of a new address bus tenure. The MSC8103 asserts this signal when one of

its internal bus masters (SC140 core or DMA controller) begins an address tenure. When the

MSC8103 senses this pin being asserted by an external bus master, it responds to the address bus

tenure as required (snoop if enabled, access internal MSC8103 resources, memory controller

support).

AACK

Input/Output

Address Acknowledge

A bus slave asserts this signal to indicate that it identified the address tenure. Assertion of this signal

terminates the address tenure.

ARTRY

Input

Address Retry

Assertion of this signal indicates that the bus transaction should be retried by the bus master. The

MSC8103 asserts this signal to enforce data coherency with its internal cache and to prevent

deadlock situations.

DBG

Input/Output

Output

Input

Data Bus Grant2

An output when an internal arbiter is used. The MSC8103 asserts this pin as an output to grant data

bus ownership to an external bus master.

An input when an external arbiter is used. The external arbiter should assert this pin as an input to

grant data bus ownership to the MSC8103.

DBB

IRQ3

Input/Output

Output

Input

Data Bus Busy1

The MSC8103 asserts this pin as an output for the duration of the data bus tenure. Following a TA,

which terminates the data bus tenure, the MSC8103 deasserts DBB for a fraction of a bus cycle and

then stops driving this pin.

The MSC8103 does not assume data bus ownership while DBB is asserted by an external bus

master.

Interrupt Request 31

One of the eight external lines that can request a service routine, via the internal interrupt controller,

from the SC140 core.

D[0–31]

Input/Output

Data Bus Most Significant Word

In write transactions the bus master drives the valid data on this bus. In read transactions the slave

drives the valid data on this bus. In Host Port Disabled mode, these 32 bits are part of the 64-bit data

bus. In Host Port Enabled mode, these bits are used as the bus in 32-bit mode.

Table 1-5.

System Bus, HDI16, and Interrupt Signals (Continued)

Signal

Data Flow

Description

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