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MSC8103/D 数据表(PDF) 67 Page - Freescale Semiconductor, Inc |
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MSC8103/D 数据表(HTML) 67 Page - Freescale Semiconductor, Inc |
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67 / 104 page  MSC8103 Network Digital Signal Processor, Rev. 11 Freescale Semiconductor 3-1 Packaging 3 This chapter provides information about the MSC8103 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8103 is available in a 332-pin lidded flip chip-plastic ball grid array (FC-PBGA). 3.1 FC-PBGA Package Description Figure 3-1 and Figure 3-2 show top and bottom views of the FC-PBGA package, including pinouts. Table 3-1 lists the MSC8103 signals alphabetically by signal name. Connections with multiple names are listed individually by each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity are shown in this table only with their default name (asserted low). Note: The package description in this chapter applies to packages with lead-bearing and lead-free spheres. |
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