MSC8103SLASHD datasheet(38/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

1-34

Freescale Semiconductor

Signals/Connections

PD19

FCC1: TXADDR4

UTOPIA master

FCC1: TXADDR4

UTOPIA slave

FCC1: TXCLAV3

UTOPIA multi-PHY master, direct

polling

BRG1O

SPI: SPISEL

Output

Input

Output

Input

FCC1: Multi-PHY Master Transmit Address Bit 4 Multiplexed Polling

This is master transmit address bit 4.

FCC1: UTOPIA Slave Transmit Address Bit 4

This is slave transmit address bit 4.

FCC1: UTOPIA Multi-PHY master Transmit Cell Available 3 Direct

Polling

Asserted by an external UTOPIA slave PHY to indicate that it can accept

one complete ATM cell.

Baud Rate Generator 1 Output

The CPM supports up to 8 BRGs for use internally by the bank-of-clocks

selection logic and/or to provide an output to one of the 8 BRG pins.

BRG1O can be the internal input to the SIU timers. When CLK5 is

selected (see PC27 above), it is the source for BRG1O which is the

default input for the SIU timers. See the system interface unit (SIU)

chapter in the

MSC8103 Reference Manual for additional information. If

CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is

enabled (see PC26 above), the BRG1O input to the SIU timers is

disabled.

SPI: Select

The SPI interface comprises four signals: master out slave in

(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select

(SPISEL). The SPI can be configured as a slave or master in single- or

multiple-master environments. SPISEL is the enable input to the SPI

slave. In a multimaster environment, SPISEL (always an input) detects

an error when more than one master is operating. SPI masters must

output a slave select signal to enable SPI slave devices by using a

separate general-purpose I/O signal. Assertion of an SPI SPISEL while

it is master causes an error.

PD18

FCC1: RXADDR4

UTOPIA master

FCC1: RXADDR4

UTOPIA slave

FCC1: RXCLAV3

UTOPIA multi-PHY master, direct

polling

SPI: SPICLK

Output

Input

Input/ Output

FCC1: UTOPIA Master Receive Address Bit 4

This is master receive address bit 4.

FCC1: UTOPIA Slave Receive Address Bit 4

This is slave receive address bit 4.

FCC1: UTOPIA Multi-PHY Master Receive Cell Available 3 Direct

Polling

Asserted by an external PHY when one complete ATM cell is available

for transfer.

SPI: Clock

The SPI interface comprises four signals: master out slave in

(SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select

(SPISEL). The SPI can be configured as a slave or master in single- or

multiple-master environments. SPICLK is a gated clock, active only

during data transfers. Four combinations of SPICLK phase and polarity

can be configured. When the SPI is a master, SPICLK is the clock

output signal that shifts received data in from SPIMISO and transmitted

data out to SPIMOSI.

Table 1-10.

Port D Signals (Continued)

Name

Dedicated

I/O Data

Direction

Description

General-

Purpose I/O

Peripheral Controller:

Dedicated I/O

Protocol

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