MSC8103SLASHD datasheet(5/104 Pages) FREESCALE

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MSC8103 Network Digital Signal Processor, Rev. 11

Freescale Semiconductor

1-1

Signals/Connections

The MSC8103 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and

Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and

references the table that gives details on multiplexed signals within each group. Figure 1-1 shows MSC8103

external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are

multiplexed. Because the parallel I/O design supported by the MSC8103 communications processor module

(CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered

sequentially.

Table 1-1.

MSC8103

Functional Signal Groupings

Functional Group

Number of Signal

Connections

Detailed Description

Power (VCC, VDD, and GND)

Table 1-2 on page 1-4

Clock

Table 1-3 on page 1-4

Reset, configuration, and EOnCE

Table 1-4 on page 1-5

System bus, HDI16, and interrupts

133

Table 1-5 on page 1-7

Memory controller

Table 1-6 on page 1-13

CPM input/output parallel ports

Port A

Table 1-7 on page 1-16

Port B

Table 1-8 on page 1-21

Port C

Table 1-9 on page 1-24

Port D

Table 1-10 on page 1-33

JTAG test access port (TAP)

Table 1-11 on page 1-36

Reserved (denotes connections that are always reserved)

Table 1-12 on page 1-36

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